In general, a ferroelectric random access memory(FeRAM) device is nonvolatile and the data stored in the FeRAM device are not removed in power off. However, if the thickness of the capacitor is very thin, switching polarization is occurred fast so that the FeRAM device is able to read out the data therefrom or write the data therein with high speed and low voltage. The FeRAM device may constitute memory cells in which each memory cell is comprised of a transistor and a ferroelectric capacitor so that it is applicable to semiconductor memory device with high density. There are typically SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT), Pb(ZrTi)O.sub.3 (PZT) as ferroelectric films, (Ba,Sr)TiO.sub.3 as a dielectric film, and PbTiO.sub.3 and (Pb,La)TiO.sub.3 as pyroelectric films respectively.
FIG.1 is a cross-sectional view for illustrating a method for fabricating the semiconductor memory device.
Referring to FIG. 1, in order to define an active region, a field oxide layer 11 is formed on a selected portion of a semiconductor substrate 10. A gate insulating layer 12 and a conductive layer 13 for gate electrode are successively deposited at the active region of the semiconductor substrate 10. Selected portions of the conductive layer 13 for gate electrode and the gate insulating layer 12 are patterned thereby forming a gate electrode 14. Impurities are ion-implanted to both sides of the gate electrode 14, thereby forming source and drain regions 15a, 15b. Then, a transistor is completed. A first intermetal insulating layer 16 is deposited on the semiconductor substrate 10 in which the transistor is formed, and the first intermetal insulating layer 16 is etched to expose the drain region 15b thereby forming a contact hole within the first intermetal insulating layer 16. So as to contact with the exposed drain region 15b, a bit line 17 is formed within the contact hole and on the first intermetal insulating layer 16. A second intermetal insulating layer 18 is formed on the first intermetal insulating layer 16 in which the bit line 17 is formed. The second intermetal insulating layer 18 and the first intermetal insulating layer 16 are etched to expose the source region 15a of the transistor thereby forming a contact hole. Next, a plug 19 is formed such that the contact hole is buried. The plug 19 is formed of polysilicon material. A glue layer 20, a metal film 21 for lower electrode, a dielectric layer 22 and a metal film 23 for upper electrode are successively deposited on the plug 19 and the second intermetal insulating layer 18. The metal film 23 for upper electrode, the dielectric layer 22, the metal film 21 for lower electrode and the glue layer 20 are patterned to contact with the plug 19 thereby forming a capacitor 24. The dielectric layer 22 can be formed of ferroelectric film, high dielectric film or pyroelectric film.
However, since the plug 19 connecting the source region 15a and the capacitor 24 is made of polysilicon, layers formed on the plug 19, i.e. the glue layer 20, the metal film 21 for lower electrode, the dielectric layer and the metal film 23 for upper electrode have polycrystalline structures. Thus, volatile components i.e. Pb, Bi, O in the dielectric layer 22, are diffused to the metal film 21 for lower electrode and the glue layer 20 through a grain boundary of the dielectric layer 22 and the metal film 21 for lower electrode. Thus, characteristics of the metal film 21 for lower electrode and the glue layer 20 are degraded. Since, the volatile components of the dielectric layer 22 are diffused, dielectric characteristic of dielectric layer is degraded.